The present invention relates to forming a wafer level chip scale package, and more particularly to forming a wafer level chip scale package that avoids mechanical grinding in the fabrication process.
The following two U.S. patents and U.S. patent publication relate in general to the methods of fabrication of chip level packages utilizing wafer level fabrication methods.
U.S. Pat. No. 6,072,236 dated Jun. 6, 2000, issued to S. Akram et al. discloses a wafer level process utilizing micromachining to fabricated chip scale packages.
U.S. Pat. No. 6,468,892B1 dated Oct. 22, 2002, issued to M. H. Baker et al. describes a method utilizing a solder mask at the wafer level for forming bumps on chip scale packages.
U.S. Patent Application Publication US2002/002725A1 dated Mar. 7, 2002, issued to L. D. Kinsman et al. describes a method for fabricating a chip scale package utilizing wafer level processing.
With a need for smaller semiconductor packages, there are now processes for packaging of semiconductor integrated circuits, or dies, at the wafer level. Such processes are commonly and collectively referred to as wafer level chip scale packaging, and the resultant package is referred to as a wafer level chip scale package, (WL-CSP).
With reference to FIGS. 1 and 2A-E, an example of a wafer level chip scale packaging process 100 is now described. After components, circuitry and pads have been fabricated on a wafer 205 by processes, as will be known to one skilled in the art, the packaging process 100 starts 105 with providing 110 the wafer 205 with metal pillars 210 formed on the die pads 212, or under bump material. FIG. 2A shows the wafer 205 with the metal pillars 210 formed on the die pads 212.
U.S. patent application Ser. No. 09/564,382 by Francisca Tung, filed on Apr. 27, 2000, titled xe2x80x9cImproved Pillar Connections for Semiconductor Chips and Method of Manufacturexe2x80x9d, and Continuation-In-Part U.S. patent application Ser. No. 09/843,248 by Francisca Tung filed on Apr. 26, 2001, titled xe2x80x9cImproved Pillar Connections for Semiconductor Chips and Method of Manufacturexe2x80x9d, and assigned to a common assignee as this patent application, teaches forming at least some of such pillar structures as described herein. These patent applications are incorporated herein by reference.
A layer of coating material 215 such as mold compound, encapsulant epoxy, such as underfill coating material, or photo imageable material, such as benzocyclobutene (BCB) or polyimide, is then applied 115 over the wafer 205 with the metal pillars 210 covered by the coating material 215, as shown in FIG. 2B. The layer of coating material 215 is applied with a spin coating process. Typically, two layers of material each with a thickness of about 40-50 micrometers or microns (um) are applied to produce the resulting layer of coating material 215 with a thickness of about 100 um. The coating material should be no more than 10 um thick on the copper pillars 210, and the layer of coating material 213 is then cured.
After curing, the excess coating material on the copper pillars 210 is ground 120 away using mechanical grinding, employing abrasive compounds on grinding machines, by Okamoto Corporation of USA or Kemet International Limited of the UK, and using a poromeric polishing pad. Grinding 120 continues until the excess coating material is removed and the upper surfaces 220 of the copper pillars 210 are exposed. The ground wafer is shown in FIG. 2C.
Next a layer of gold 225 is formed 125 on the upper surfaces 220 by, for example, electroplating, as shown in FIG. 2D; and solder balls 230 are attached 130 to the layer of gold 225. Equipment by manufacturers including OKI, Casio, Fujitsu, all of Japan can be used to attach the solder balls. It will be appreciated by those skilled in the art that a subsequent reflow process causes the solder balls 230 to melt and adhere to the layer of gold 225. The wafer level packaging process 100 then ends 135. After the process 100, the bumped wafer 235 is diced to singulate the WL-CSPs.
During the grinding step 120, the wafer 205 is subjected to severe mechanical stress, and can result in micro-cracks in the wafer. Hence, a disadvantage of the process of making WL-CSPs using mechanical grinding is the potential of adverse reliability caused by micro-cracks. Another disadvantage of mechanical grinding is that grinding is slow. Yet another disadvantage is the need to invest in grinding equipment and an associated supply of grinding consumables.
Since only the upper surfaces of the layer of gold are exposed, the surface area of the gold layer to which the solder balls 230 can adhere is limited. Hence, another disadvantage is the limited surface area of the layer of gold to which the solder balls can adhere, as this can adversely affect the reliability of the WL-CSP.
The spin coating process is slow, and in addition, two spin coating operations are required to obtain a coating with the required thickness. In addition, the spin coating process wastes approximately 85% of the coating material that is disposed on the wafer 205. Therefore, still another disadvantage of the process described is the use of spin coating, which is both slow and expensive.
The present invention seeks to provide a method for forming a wafer level chip scale package and a package formed thereby, which overcomes or at least reduces the abovementioned problems of the prior art.
Accordingly, in one aspect, the present invention provides a method for forming a wafer level chip scale semiconductor package, the method comprising the steps of:
providing a semiconductor wafer having a surface with a plurality of pads, wherein each of the pads has a conductor extending a first predetermined distance away from the surface;
forming a layer of conductive etch resistant material on free ends of the conductors;
disposing electrically insulating material on the surface of the semiconductor wafer, wherein the layer of electrically insulating material has an exposed surface a second predetermined distance from the surface of the semiconductor wafer, wherein the second predetermined distance is less than the first predetermined distance, and wherein portions of the electrically insulating material are disposed on the layer of conductive etch resistant material and on side surfaces of at least some of the conductors; and
removing substantially all the portions of the electrically insulating material disposed on the layer of conductive etch resistant material and on the side surfaces of some of the conductors.
In another aspect, the present invention provides a wafer level chip scale package comprising:
a semiconductor die having a plurality of pads on a surface;
conductors coupled to and extending a first predetermined distance from the plurality of pads;
an etch resistant layer on free ends of the conductors;
a layer of insulation on the surface, the layer of insulation having an exposed surface a second predetermined distance from the surface, wherein the second predetermined distance is less than the first predetermined distance; and
reflowable material adhering to the etch resistant layer and to at least portions of side surfaces of substantially all of the conductors.
In yet another aspect the present invention provides a method for forming a wafer level chip scale semiconductor package, the method comprising the steps of:
providing a semiconductor wafer having a surface with a plurality of pads, wherein each of the pads has a conductor extending a first predetermined distance away from the surface;
disposing reflowable material on free ends of the conductors;
disposing electrically insulating material on the surface of the semiconductor wafer, wherein the layer of electrically insulating material has an exposed surface a second predetermined distance from the surface of the semiconductor wafer, wherein the second predetermined distance is greater than the first predetermined distance; and
selectively removing at least a portion of the electrically insulating material such that the exposed surface is a third predetermined distance from the semiconductor wafer, wherein the third predetermined distance is greater than the first predetermined distance and less than the second predetermined distance.
In still another aspect the present invention provides a wafer level chip scale package comprising:
a semiconductor die having a plurality of pads on a surface;
conductors coupled to and extending a first predetermined distance from the surface of the semiconductor die;
reflowable material attached to the free ends of the conductors; and
a layer of insulation on the surface of the semiconductor die and surrounding the conductors, the layer of insulation having an exposed surface a second predetermined distance from the surface of the semiconductor die, wherein the second predetermined distance is greater than the first predetermined distance.